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  1. #1
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    Motherboard Chipsets Map












    (

    ) northbridge

    .


    • (northbridge)



      amd



      AMD

      (memory controller )





    • amd









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  2. #2
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    : Motherboard Chipsets Map

    RAM

    TIMING

    (MATRIX) STUCK

    FRIST INPUT FRIST OUTPUT )FIFO)



    .




    DUAL CHANNAL .










    IDALE .


    the memory controller and the RAM memory

    dual channal












    .






    SLOT





    RDRAM ( )





    DDR3






    SDRAM



    DDR1



    DDR2









    1 .











    C1 - C2 -C3 -C6 -C7 - dd
    d1 -d2 -d3 -d4

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  3. #3
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    : Motherboard Chipsets Map

    (NORTHBRIDGE)




    memory address space
    I/O address space
    interrupts


    .

    the front-side bus (read or write memory)





    It uses some pins to transmit the physical memory address it wants to write or read, while other pins send the value to be written or receive the value being read. An Intel Core 2 QX6600 has 33 pins to transmit the physical memory address (so there are 233 choices of memory locations) and 64 pins to send or receive data (so data is transmitted in a 64-bit data path, or 8-byte chunks). This allows the CPU to physically address 64 gigabytes of memory (233 locations * 8 bytes) although most chipsets only handle up to 8 gigs of RAM.






    northbridge ( )

    amd .

    Physical memory addresses

    ( memory-mapped I/O)



    http://en.wikipedia.org/wiki/Memory-mapped_IO

    Physical memory addresses :

    video cards
    PCI cards
    BIOS






    (NORTHBRIDGE)






    busses (controllers) EIDE devices .





    northbridge & southbridge

    northbridge & southbridge link





    northbridge .

    large heat sink








    AGP I/O PORT

    .

    PCI Express AGP .

    NORTHBRIDGE






    SHORT OPEN

    .






    SHORT







    OPEN

    .





    .

    Voltage Regulator

    .





    ( RZ 848).



    ( )



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  4. #4
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    : Motherboard Chipsets Map

    South Bridge




    ICH (I/O Controller Hub) .

    (controlling I/O devices) .



    1- Parallel and SerialATA ports

    -2 USB ports

    3- On-board audio

    4- On-board LAN

    5- PCI bus

    6- Real time clock (RTC)

    -7 CMOS memory



    On-board audio




    (audio controller)

    ( codec= coder/decoder) .

    On-board LAN




    (phy= physical)



    1- (bios)

    2- ( Super I/O chip)

    serial ports, parallel port and floppy disk drive.









    usb .

    southbridge






    sis ati msi945









    865 rz




    .





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  5. #5
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    : Motherboard Chipsets Map

    Super I / O





    Super I/O chipset does your system health check.

    Super I / O







    Super I / O




    • ps/2
    • paralle port





    33 power on /off



    5 soltek 848 8

    pci





    • LPC (Low Pin Count) Interface
    • Hardware Monitor Controller
    • Fan Speed Controller
    • Flash-ROM Interface
    • SmartGuardian Controller
    • IEEE1284 Parallel Port
    • Floppy Disk Controller
    • Game Port
    • 56 General Purpose I/O Pins
    • Input mode supports switch de-bounce
    • Output mode supports one set of programmable LED blinking periods
    • Watch Dog Timer
    • Times out the system, based on a user-programmable time-out period
    • Time resolution 1 minute, maximum 255 minutes
    • Dedicated Infrared pins
    • Compliant with IrDA 1.4 for VFIR
    • Single 48MHz Clock Input
    • Single 3.3V Power Supply
    • 128-pin LPQF





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  6. #6
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    : Motherboard Chipsets Map

    clock generator



    (timming signal)

    .

    .





    (clock generator)



    http://www.qariya.com/modules.php?na...getit&lid=2216

    http://www.qariya.com/vb/showpost.ph...65&postcount=5



    l;et lc







    clock generator




    • CPU
    • FSB
    • GPU
    • RAM



    southchip
    • system clock frequency
    • reset signal



    control signal bus.



    rest signal






    a chipset, connected to the CPU, wherein the CPU communicates with a
    peripheral of the computer main board through the chipset;

    a clock generator, connected to the chipset, providing the chipset with a
    system clock frequency for operating the computer main board, wherein the
    CPU controls the clock generator through the chipset, and the clock
    generator is controlled through a first control signal bus; and

    a reset signal generator, connected to the chipset and controlled by the
    CPU through the chipset, which provides the chipset with a reset signal,
    wherein the reset signal generator is controlled through a second control
    signal bus, such that when the clock generator needs to change the system
    clock frequency according to a command from the CPU, the reset signal
    generator activates the reset signal simultaneously for changing a clock
    frequency of the peripheral from a current frequency to an intended
    frequency with respect to the svstem clock frequency where the intended
    frequency can be repeatedly reset until the intended frequency matches in
    ratio to the system clock frequency and the reset signal remains
    activation until the system clock frequency is completely changed to a new
    setting.

    6. The circuit of claim 5, wherein the circuit further comprises a status
    latch for storing a status parameter set by the CPU as soon as the system
    clock frequency is changed, wherein the set status parameter is retrieved
    by the chipset from the status latch to determine a ratio of the system
    clock frequency to a clock frequency of the peripheral after the computer
    main board is restarted.

    7. The circuit of claim 5, wherein the first control signal bus includes an
    I2 C bus.

    8. The circuit of claim 7, wherein the second control signal bus includes
    an I2 C bus.

    9. The circuit of claim 8, wherein the chipset comprises an I2 C bus
    interface that is used by the CPU to control the clock generator and the
    reset signal generator.

    10. A method for switching system clock of a computer main board, the
    method comprising:

    providing a CPU;

    providing a clock generator, for generating a system clock frequency;

    sending out a command from the CPU to the clock generator to change the
    system clock frequency;

    sending out a reset signal from the clock generator as soon as the clock
    generator starts to change the system clock frequency wherein the reset
    signal resets a clock frequency of a peripheral from a current frequency
    to an intended frequency with respect to the system clock frequency where
    the intended frequency can be repeatedly reset until the intended
    frequency matches in ratio to the system clock frequency, and

    canceling the reset signal by the clock generator as soon as the system
    clock frequency is changed to a new setting.

    11. The method of claim 10, wherein the method further comprises providing
    a status latch for storing a status parameter set by the CPU as soon as
    the system clock frequency is changed, wherein the set status parameter is
    retrieved by the chipset from the status latch to determine a ratio of the
    system clock frequency to a clock frequency of the peripheral after the
    computer main board is restarted.

    12. A method for switching system clock of a computer main board, the
    method comprising:

    providing a CPU;

    providing a clock generator, for generating a system clock frequency;

    sending out a command from the CPU to the clock generator to change the
    system clock frequency;

    sending out a reset signal from a reset signal generator as soon as the
    clock generator starts to change the system clock frequency, wherein the
    reset signal resets a clock frequency of a peripheral from a current
    frequency to an intended frequency with respect to the system clock
    frequency where the intended frequency can be repeatedly reset until the
    intended frequency matches in ratio to the system clock frequency, and

    canceling the reset signal from the reset signal generator as soon as the
    system clock frequency is changed to a new setting.

    13. The method of claim 12, wherein the method further comprises providing
    a status latch for storing a status parameter set by the CPU as soon as
    the system clock frequency is changed, wherein the set status parameter is
    retrieved by the chipset from the status latch to determine a ratio of the
    system clock frequency to a clock frequency of the peripheral after the
    computer main board is re








    clk

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  1. []
    zahret el ferdaws Rise Advertise
    : 0
    : 19-08-2013, 16:28
  2. Aya Adel
    : 1
    : 07-03-2011, 23:11
  3. ...... +
    Eng Amr Adel
    : 0
    : 08-12-2009, 22:11